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VOLUME 07,  September 2016

Article-08690

Real time active surveillance system with night vision capability using OpenCV and Raspberry pi

SABIHA MOHAMMED SABIULLAH, CH HARIPRASAD

Article-06682

DESIGN AND DEVELOPMENT OF ARM ABSED ELECTRONIC TEST EVALUATION SYSTEM FOR RTO

S S SALOKHE, U L BOMBALE

Article-06676

Voice Activated Page Turner for People with Limited Bilateral Upper Extreme Functionality

K. PADMA VASAVI

VOLUME 07,  August 2016

VOLUME 07, June 2016

Article-06678

DESIGN AND ANALYSIS OF DMA CONTROLLER FOR SYSTEM ON CHIP BASED APPLICATIONS

A MURALI, BONU RAMA KRISHNA, KUNA DURGA PRASAD

Article-05675

DESIGN OF FPGA BASED 8 BIT RISC PROCESSOR

S.V. KULKARNI, A.I. NADAF, P.P. SHAH, M.K. BHANARKAR

VOLUME 07, May 2016

 Article-04662

FLEXIBLE VLIW PROCESSOR IMPLEMENTATION ON FPGA AND ITS APPLICATION

Bedare H.M., Kureshi A.K

Article-05672

VHDL IMPLEMENTATION OF AN ENCRYPTED IMAGE TRANSMISSION SYSTEM

ADITHYA SABARISH S, KAUSHIK C A, PRADHEEP S, ARVIND P, PREMALATHA B

 Article-05673

ENERGY EFFICIENT MOS DIGITAL CIRCUIT FOR LOW POWER VLSI DESIGN VIVEK JAIN, SANJIV TOKEKAR, VAIBHAV NEEMA

 Article-04666

HIGHER ORDER MUX BASED VEDIC MULTIPLIER FOR IMAGE PROCESSING APPLICATION

SWAPNA K, MAHESH NEELAGAR

  Article-04664

DESIGN AND IMPLEMENTATION OF AN EMBEDDED COLOR BASED CITRUS CLASSIFICATION SYSTEM

TODALI BHAGYASHRI B, MAHESH NEELAGAR, T.C.THANUJA

VOLUME 07, March-April 2016

Article-04461

AUTOMOBILE ON BOARD DIAGNOSTIC SYSTEMS

KARTHIK.M, S.SUJA

VOLUME 07, January – February 2016

Article-11642

FLOATING POINT ARCHITECTURE BASED ON FPGA

M.THAMARAI SELVAN1,N.PASUPATHY2, K.ASHOK KUMAR3

Article-01649

REVIEW ON WIRELESS SENSOR NETWORK

NIMISHA A RAI, JAYSHREE S SONAWANE

Article-01648

VLSI IMPLEMENTATION OF 12-BIT SAR ADC OPTIMIZING DYNAMIC POWER

C ASHOK KUMAR, B K MADHAVI, K LALKISHORE

VOLUME 06, October 2015

Article-09627

 Optimization and Simulation of Two Stage Operational Amplifier using 180nm Technology

PRATIKA CHHATWAL, SHUBHAM TAYAL

Article-09635

Area-Efficient Low Power OTA-C Filter for Biomedical Applications

TAHSEEN FATMA, V N RAMAKRISHNAN

Article-09634

FIR Filter Design and Implementation using Remez Exchange Algorithm with Multipliers and Adders

Vadapalli Siddhartha

Article-09641

DESIGN AND ANALYSIS OF POWER EFFICIENT 9T ADIABATIC SRAM CELL

NISHA YADAV, SUNIL JADAV , PARDEEP

VOLUME 06, September 2015

Article-08614

DESIGN OF HIGH THROUGHPUT AND HIGH SPEED HYPERCUT PACKET CLASSIFICATION

ASHWINI CHOUGALA, T.C. THANUJA, USHA S

VOLUME 06, August 2015

Article-08622

IMPLEMENTATION OF COACH GUIDANCE DISPLAY SYSTEM

SIRISHA KUNISETTI

Article-06598

PERFORMANCE OPTIMIZATION APPROACH FOR ADDER IN FOLDING TREE ARCHITECTURE

K RANJITHKUMAR, TRV ANANDHARAJAN

Article-06588

ZIGBEE AND PLC BASED SMART HOME ENERGY MANAGEMENT SYSTEM

B RAJASEKARAN, R THIRUNAVUKKARASU, G MURALI, M BOOPATHI

VOLUME 06, July 2015

Article-07609

COMMUNICATION PROTOCOL FOR NETWORKED EMBEDDED SYSTEM

PRADIP RAM SELOKAR, P. T. KARULE

Article-05577

PERFORMANCE EVALUATION OF HHT AND LOW PASS FIR FILTER FOR IMAGE STABILIZATION USING VHDL

JINSHA KRISHNAN, K.V.KARTHIKEYAN

VOLUME 06, June 2015

Article-06601

­­­­­­­­AN EFFICIENT VOLTAGE COMPARATOR USING PREAMPLIFICATION PROCESS

R.PRASHANTH, K.GOMATHY

Article-07608

FPGA Based Implementation of Scaling Method for Curve Based Cryptography

SHWETHA M.N, LEELAVATHI

Article-06589

CONGESTION CONTROL FRAMEWORK IN WIRELESS MULTIMEDIA SENSOR NETWORKS

J SARAVANA KUMAR, S.KANNAN, N MANIKANDA DEVARAJAN, G SURESH KUMAR

Article-06596

VLSI DESIGN OF LOW ENERGY MODELING FOR NETWORK ON CHIP (NoC) APPLICATIONS

JEEVA ANUSHA, V.THRIMURTHULU

Article-06597

 VLSI HARDWARE MODELING OF DYNAMIC RNS STRUCTURE FOR HIGHEND COMPUTATIONS

GANJI SARIKA YADAV, V.THRIMURTHULU, S.ALI ASGAR

Article-05586

Low-Complexity Low-Latency Architecture for Matching of Data Encoded with Hard Systematic Error-Correction Codes

SANTOSHKUMAR

VOLUME 06, May 2015

Article-05583

VLSI MODELING OF SENSITIZATION INPUT VECTOR EFFECT ON PROPAGATION DELAY FOR 32 NM CMOS DESIGNS

SUPRIYA KASALA, S.ALI ASGAR, V.THRIMURTHULU

Article-05580

An Area-Efficient Carry Select Adder Designed by Using Transmission Gate

JISMI.T.A, NITHIN JOSE K

Article-05579

AN EXHAUSTIVE REVIVES APPROACH USING IOT FOR SMART TRAFFIC FLOW PREDICTION

KIRAN V, ESHWARAIAH R

Article-03547

PERFORMANCE COMPARISON OF DIFFERENT POWER GATING TECHNIQUES IN AFPL-PCR

C PREETHIBHA, S R PAVITHRA, NEENU SEBASTIAN

Article-04565

SPEED CHECKER ON HIGHWAYS FOR ACCIDENT AVOIDANCE AND DETECTION

PINAKI SATPATHY, JOYDEEP MANDAL, KANCHAN KR. PAUL, KALLOL MONDAL, PRITISH KR. NASKAR

Article-04564

DESIGN OF LOW POWER MOS SRAM CELL USING 10 TRANSISTORS

VERTIKA SARKARI, AJITA PATHAK

Article-04568

DESIGN OF DC-DC CONVERTER FOR SOLAR APPLICATION

M SATYA NARAYANA RAO, M MURALI KRISHNA

VOLUME 06, April 2015

Article-04572

DESIGN OF UNIVERSAL CANISTER CONTROL MODULE USING ARM MICROCONTROLLER

SREE LAKSHMI ELE, VENKATARATNAM. P, ARUN BABU. A, RAJSHEKAR.B

Article-12522

DESIGN FLOW CYCLE AND SIMULATION OF LOAD MOVER

ASHISH MISHRA, ARSHAD JAVED, KARAN BHARGAVA, KAUSTUBH TANMANE, HARDIK SHAH 

 

VOLUME 06, March 2015

Article-03544

A survey of sensorized glove for rehabilitation purpose

P D NANDNIKAR, M S NAGMODE, M N ANNADATE

Article-03543

A Review on Water Quality Monitoring System

M N BARABDE, S R DANVE

 

VOLUME 06, February 2015

Article-01530

LOWPOWER ANALYSIS OF FLP-FLOP USING GDI TECHNIQUE

ABINAYA.A

Article-01532

 EFFICIENT POWER CONSUMPTION AND COMPLEXITY EFFECTIVE DESIGN OF NARROWBAND USING FRM

N.SUBBULAKSHMI

Article-01531

REVIEW PAPER ON AN IMPLEMENTATION OF RIJNDAEL ALGORITHM ON FPGA

M K MANKAR, M V VYAWAHARE

Article-01529

DECIMAL FLOATING POINT IMPLEMENTATION USING VERILOG HDL

VINOD KAPSE, PUNEET BHARADWAJ, Y. ARUNIKA RAO

Article-01526

FPGA BASED WIRELESS SENSOR NETWORK NODE: SURVEY

JUWAIRIYAH SARKHAWAS, P.D.KHANDEKAR

VOLUME 06, January 2015

Article-12519

A NOVEL DESIGN APPROACH TO INCREASE THE SPEED OF VLSI CIRCUITS IN MIXED-SIGNAL ENVIRONMENT

R.PRAKASH RAO, B.K.MADHAVI

Article-12521

High Performance Carry Skip Adder using Reversible Logic

MONALISA BHOWMIK, SUHEL RANJAN MONDAL, RAZIA SULTANA, SANTANU MAITY, SURAJIT MUKHERJEE

VOLUME 05, December 2014

Article-08402  

MULTIPLE ERROR RECOVERY TECHNIQUE FOR TMR SYSTEMS IN SAFETY CRITICAL APPLICATIONS

ANJALI S, PRAVEENA S KAMMATH

Article-11504 

VLSI IMPLEMENTATION OF A FLEXIBLE AND SYNTHESIZABLE FFT PROCESSOR

RAMAKOTIREDDY THUGUTLA, Y V BHASKAR REDDY, K. VEERASWAMY, A. M. PRASAD

Article-11506 

VLSI IMPLEMENTATION OF IEEE754-2008 STANDARD FOR FINANCIAL TRANSACTIONS

T.MURALIKRISHNA, C.SRINIVASA MURTHY

Article-10488 

NETWORKING IN AUTOMOBILE USING CAN PROTOCOL

R.SIVA BABU, V.NARASIMHA RAO

VOLUME 05, November 2014

Article-11493 

IMPLEMENTATION OF COMPRESSED IMAGE USING DWT ON FPGA

D.BINDU TUSHARA, P.A.HARSHA VARDHINI, N.RANGANADH

Article-11498 

 ATMOSPHERE MONITORING AND AUTO CONTROL USING ARM BASED MULTIPLE MASTERS ECSN

 G.VENKATARAMAIAH, S.LOKESH

Article-11497

  HIGHLY SECURED RAILWAY RESERVATION USING BIOMETRIC TECHNOLOGY

 Y.NAGAMUNEENDRA REDDY, LAKSHMAN RAMAMURTHY. K

Article-11489

MIL-STD 1553 REMOTE TERMINAL PROTOCOL PROCESSOR IMPLEMENTATION USING FPGA

VISHNU PRASAD S, SUNIL JACOB, VIVEKANAND V

Article-10482

COMPUTING TWO PATTERN TEST CUBES FOR TRANSITION PATH DELAY FAULTS

B.SRENIMA, P.SOUNDARYA MALA

Article-11492

DESIGN OF 9 BIT SAR ADC USING HIGH SPEED AND HIGH RESOLUTION OPEN LOOP CMOS COMPARATOR IN 180NM TECHNOLOGY WITH R-2R DAC TOPOLOGY

AKHIL A, SUNIL JACOB

Article-11496

HDL Design for Tera Hertz Clock based 2e23-1 Tera Bits per Second (Tbps) PRBS Design for Ultra High Speed Wireless Communication Applications/Products

P.N.V.M SASTRY, S.VATHSAL, D.N.RAO

Article-11491

REALISATION OF VEDIC MULTIPLIER USING URDHVA TIRYAKBHAYAM SUTRA

N. BHAGYA LAKSHMI, B. VIJAYA LAKSHMI

Article-09450

Floating point addition using low power CSA

DILJITH MURALY, SUNIL JACOB, K PADMAKUMAR

Article-11495

Improvement in latency through the use of common buffer pool in routing node of 2D Mesh NoC

SHILPA P. KODGIRE, U.D.SHIURKAR

Article-10483

MULTIPROCESSOR SYSTEM-ON-CHIP IMPLEMENTATION FOR NETWORK-ON-CHIP COMMUNICATION WITH 5-BIT DATA LINE

M.V.V.PRASANTHI, V.SREEVANI

Article-10486

AREA EFFICIENT LOW COMPLEXITY QPP INTERLEAVER

NITHIN JOSE. K, AMRUTHA.V

Article-10479

SURVEY ON MEMORY YIELD PREDICTION USING PHYSICS BASED 2-D DEVICES

NIKHIL RAJ, GNANA SHEELA K

Article-07386

AN EFFICIENT LOW POWER DESIGN FOR ASYNCHRONOUS DATA SAMPLING IN DOUBLE EDGE TRIGGERED FLIP-FLOPS

NINU ABRAHAM, VINOJ P.G

Article-08393

IMPLEMENTATION OF ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING TRANSCEIVER ON FPGA

AMRUTHA A, SUNIL JACOB, VRINDA V GOPAL

Article-09447

FPGA DESIGN OF FAULT TOLERANT STEPPER MOTOR AND DC MOTOR CONTROLLER USING TMR FOR SPACE ROBOTIC APPLICATIONS

NAVEEN RAJ, SUNIL JACOB

Article-10487

LOW-POWER DUAL-EDGE TRIGGERED CROSS-COUPLED SENSE -AMPLIFIER FLIP-FLOP

P.DURGA, A.VENKATA KRISHNA

Article-10473

REALIZATION OF XOR AND XNOR GATES USING QCA BASIC GATES

SUBHASHEE BASU

Article-10474

HIGH PERFORMANCE ADDER USING RESIDUE NUMBER SYSTEM

K.V.LALITHAV.SAILAJA

 

VOLUME 05, October 2014

Article-10470

DESIGN AND PERFORMANCE ANALYSIS OF DOUBLE-PRECISION FLOATING POINT MULTIPLIER USING URDHVA TIRYAGBHYAM SUTRA

Y SRINIVASA RAO, T SUBHASHINI, K RAMBABU

Article-10468

 BUILT-IN GENERATION OF FUNCTIONAL BROADSIDE TEST FOR ISCAS-85 C432         

CH. NAVEEN KUMAR , N.M. RAMALINGESWARARAO

Article-10467

DESIGN OF CARRY-LOOK-AHEAD ADDER USING REVERSIBLE LOGIC IMPLEMENTATION IN QCA

SUBHASHEE BASU, ADITI BAL, SUPRIYA SENGUPTA

Article-09457

ANDROID MOBILE PHONE CONTROLLED BLUETOOTH ROBOT USING ARM7 MICROCONTROLLER

B.RAJESH PRASAD, P.SOUNDARYA MALA

Article-09454

LOW-POWER, LOW-TRANSITION TEST PATTERN GENERATOR IN LOGIC BIST SCHEMES

G. NAGA SEETA, CH.SIRISHA

Article-09458

Design of OFDM Based Acoustic Communication System using FPGA

DIVYA MOKARA, A.S.SRINIVASA RAO, R.V.KIRAN KUMAR

Article-10465

HIGH-SPEED SUPERIOR BI-ROTATIONAL CORDIC USING QUADRANT AMENDMENT WITH PRE-SCALED STRUCTURAL DESIGN

K JAYARAM KUMAR, P SOUNDARYA MALA

Article-09432

THE PERFORMANCE IMPROVEMENT AND REDUCING BIT ERROR RATE ON WIRELESS DEEP FADING ENVIRONMENT RECEIVERS

M.KEERTHI, D.SATYANAARAYANA

Article-09424

A NOVEL METHOD FOR SNR ESTIMATION SCHEME FOR SECURE COMMUNICATION OVER FADING CHANNEL

 MUNWAR ALI SHAIK, SK.MD.SHAREEF

Article-09421

AN EFFICIENT APPROACH FOR IMPROVING PERFORMANCE ON WIRELESS NETWORKS USING SMART ANTENNAS

M.KRISHNA REDDY, K.SUNEETHA

Article-09423

AN ADVANCED SELECTION COOPERATION WITH ARQ IN DELAY-TRADEOFF  WIRELESS NETWORKS

SHAIK MOHAMMED HUSSAIN , K. ROJAMANI

Article-09420

NOVEL METHOD FOR DISTRIBUTED SPACE-TIME-CODED PROTOCOLS FOR EXPLOITING COOPERATIVE DIVERSITY IN WIRELESS NETWORKS

ILYAS AHMED, K.ROJAMANI

Article-09422

An Efficient Approach for Design of Optical Wireless IR-UWB Systems for Single User Detection

SHAIK.MAHABOOB SUBANI, KADIYAM SUNEETHA

Article-09431

A Novel Technique for Human Identification through Finger Images

J.YEDUKONDALU, SHAIK BASHEERA

Article-09426

A  RELAY BASED APPROACH FOR   TWO-WAY COMMUNICATION IN OFDM NETWORK PERFORMANCE IMPROVEMENT

U.SAI KISHORE  KUMAR, SK.MD.SHAREEF

Article-09455

DESIGN AND ANALYSIS OF FAST ADDITION MECHANISM FOR INTEGERS USING QUATERNARY SIGNED DIGIT NUMBER SYSTEM

G.MANASA, M.DAMODHAR RAO, K.MIRANJI

Article-09434

High Frequency Power Optimized Ring Voltage Controlled Oscillator for 65nm CMOS Technology

NEHA K.MENDHE, M. N. THAKARE, G. D. KORDE

Article-09449

LOW POWER CURRENT COMPARISON DOMINO LOGIC FOR WIDE FAN IN GATES

K.VENKATA LAXMI, B.LAKSHMI

VOLUME 05, September 2014

Article-09444

MINIMIZATION OF TRANSITION DENSITY IN VLSI TESTING BY MULTIPLE ARRAYS OF SIC VECTORS WITH REDUCED ARCHITECTURE

T.RAJU, O.SUDHAKAR

Article-08398

A MODIFIED DOMINO LOGIC CIRCUIT FOR IMPROVED NOISE IMMUNITY AND DELAY VARIABILITY

RAVIKANT THAKUR, AJAY KUMAR DADORIA, TARUN KUMAR GUPTA

Article-09442

POWER EFFICIENT ENHANCED DUAL DYNAMIC HYBRID FLIP-FLOP

B.KAVITHA DEVI, P.V.K.CHAITANYA

Article-09439

LAYOUT DESIGNING AND OPTIMIZATION TECHNIQUES USED FOR DIFFERENT FULL ADDER TOPOLOGIES

ARPAN SINGH RAJPUT, RAJESH PARASHAR

Article-09410

IMPLEMENTATION OF HIGH PERFORMANCE BINARY SQUARER

PRADEEP M C, RAMESH S

Article-09411

 A NOVEL ARCHITECTURE FOR MAC UNIT USING REVERSIBLE LOGIC GATES

 R. SIVA SAI, C. LEELA MOHAN, M.SREELAKSHMI

Article-08400

A VHDL implementation in FPGA on Advance Encryption Standard (AES) by using Rijndael Algorithm

LAL BAHADUR

Article-09412

A MULTIBAND FLEXIBLE INTEGER-N DIVIDER BASED ON PULSE SWALLOW TOPOLOGY

O. HARISH, SK. SHAGUFTHA

Article-09413

DESIGN OF LOW POWER SEQUENTIAL CIRCUITS BY USING CLOCKED PASS TRANSISTOR FLIP FLOP

KONCHA VINAYKUMAR, ANNAPALLI RAJESH

Article-09414

SHIFT REGISTER DESIGN USING MULTI BIT FLIPFLOPS

N.MANOJKUMAR, K.PENCHALAIAH

Article-09415

A NOVEL ARCHITECTURE FOR HIGH SPEED 1-BIT FULL ADDER AT 45nm TECHNOLOGY

G. LAKSHMINARAYANA YADAV, P. SRAVANKUMAR REDDY

Article-09416

BUILT-IN GENERATION OF FUNCTIONAL BROADSIDE USING FIXED HARDWARE STRUCTURE

SADHU KRISHNA PRASAD, G. JAGADEESHWAR REDDY

Article-09435

OFDM MODULATOR FOR WIRELESS LAN (WLAN) STANDARD

K.ANISH, K.S.SAGAR REDDY

VOLUME 05, August 2014

Article-08395

DESIGN AND IMPLEMENTATION OF BCD ADDER USING INTEGRATED QUBIT GATES FOR QUANTUM APPLICATIONS

P.V.N.VISHNUPRIYA, S.SIVAPRASAD

Article-08401

IMPLEMENTATION OF 2-D TWO LEVEL DWT VLSI ARCHITECTURE

KANCHETI SIVAPRIYA, VENKATASAICHAND NANDANAVANAM

 

VOLUME 05, July 2014

Article-04307

JPEG IMAGE COMPRESSION USING DIFFERENT WAVELET TRANSFORMS ANTI FORENSICS

PAMARTHY CHENNARAO, M.NAVYA, T.PRIYANKA, R.RAVI, K. MAHESH

Article-05356

Design of Low-power and High Performance Pulse Triggered Flip-Flop

PRASANTA KUMARGORAI, S.N.SINGH

Article-07390

Design and Implementation of Efficient Adder based Floating Point Multiplier

LOKESH BHARDWAJ, SAKSHI BAJAJ

Article-07387

A Novel Architecture for Optimised Parallel Multiplier

SONIA VERMA, SAKSHI

Article-07380

VHDL IMPLEMENTATION OF UART WITH ADAPTIVE BAUD RATE GENERATOR

DEEPTI AGARWAL, NIDHI SHARMA, CHIRANJEET KUMAR

Article-05362

DESIGN OF HIGH SPEED AND AREA EFFICIENT UNSIGNED MULTIPLIER USING CBL TECHNIQUE 

RAJ KUMAR MADDHESHIYA, B.N.S. MUNDA, ANANT ANAND SINGH

Article-06373

MOBILE PHONE BASED INTERNAL APPLIANCE CONTROL USING AVR DEVELOPMENT BOARD

TEJASWINY SINGH, RAMANDEEP SINGH